| Threadmill: A post-silicon exerciser for multi-threaded processors A Adir, M Golubev, S Landa, A Nahir, G Shurek, V Sokhin, A Ziv Proceedings of the 48th Design Automation Conference, 860-865, 2011 | 53 | 2011 |
| Hardware verification using acceleration platform M Dusanapudi, W Kadry, S Kapoor, D Krestyashyn, S Landa, A Nahir, ... US Patent 8,832,502, 2014 | 18 | 2014 |
| Control flow error localization O Friedler, W Kadry, A Nahir, V Sokhin US Patent 9,251,045, 2016 | 15 | 2016 |
| Architectural failure analysis O Friedler, W Kadry, A Nahir, V Sokhin US Patent 9,569,345, 2017 | 14 | 2017 |
| Effective post-silicon failure localization using dynamic program slicing O Friedler, W Kadry, A Morgenshtein, A Nahir, V Sokhin 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 12 | 2014 |
| Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation G Papadimitriou, D Gizopoulos, A Chatzidimitriou, T Kolan, A Koyfman, ... 2016 IEEE 34th International Conference on Computer Design (ICCD), 544-551, 2016 | 10 | 2016 |
| Method and apparatus for post-silicon testing A Adir, E Bin, S Copty, A Koyfman, S Landa, A Nahir, V Sokhin, E Tsanko US Patent 8,892,386, 2014 | 10 | 2014 |
| Test generation using expected mode of the target hardware device P Sung-Boem, A Nahir, V Sokhin, W Kadry, JS Park, A Cho US Patent 9,626,267, 2017 | 8 | 2017 |
| Validation of multiprocessor hardware component P Sung-Boem, A Nahir, V Sokhin, W Kadry, JS Park, A Cho US Patent 10,528,443, 2020 | 7 | 2020 |
| Testing address translation cache H Mendelson, T Kolan, V Sokhin US Patent 11,263,150, 2022 | 6 | 2022 |
| Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification D Lee, T Kolan, A Morgenshtein, V Sokhin, R Morad, A Ziv, V Bertacco Proceedings of the 53rd Annual Design Automation Conference, 24, 2016 | 6 | 2016 |
| Improving post-silicon validation efficiency by using pre-generated data W Kadry, A Koyfman, D Krestyashyn, S Landa, A Nahir, V Sokhin Haifa Verification Conference, 166-181, 2013 | 6 | 2013 |
| Comparative study of test generation methods for simulation accelerators W Kadry, D Krestyashyn, A Morgenshtein, A Nahir, V Sokhin, JS Park, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 321-324, 2015 | 3 | 2015 |
| Post Silicon Validation of the MMU T Kolan, H Mendelson, V Sokhin, S Doron, H Theiler, S Aviv, H Hadad, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 212-217, 2021 | 2 | 2021 |
| Post-silicon validation of the ibm power9 processor T Kolan, H Mendelson, V Sokhin, K Reick, E Tsanko, G Wetli 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 999 …, 2020 | 2 | 2020 |
| Verification of atomic memory operations T Har'el Kolan, H Mendelson, V Sokhin US Patent 10,496,449, 2019 | 2 | 2019 |
| Post-Silicon Validation of the IBM POWER8 Processor T Kolan, H Mendelson, A Nahir, V Sokhin Post-Silicon Validation and Debug, 343-363, 2019 | 2 | 2019 |
| Recoverable exceptions generation and handling for post-silicon validation H Mendelson, V Sokhin, T Kolan, H Theiler, S Doron US Patent 11,226,370, 2022 | 1 | 2022 |
| Partial-results post-silicon hardware exerciser T Kolan, A Lvovsky, H Mendelson, V Sokhin US Patent 11,204,859, 2021 | 1 | 2021 |
| Automatically introducing register dependencies to tests H Mendelson, T Kolan, V Sokhin US Patent 11,194,705, 2021 | 1 | 2021 |
Amir NahirApplePreverjeni e-poštni naslov na apple.com
