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Sharad Chole
Sharad Chole
Expedera
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Title
Cited by
Cited by
Year
Programmable packet scheduling at line rate
A Sivaraman, S Subramanian, M Alizadeh, S Chole, ST Chuang, ...
Proceedings of the 2016 ACM SIGCOMM Conference, 44-57, 2016
3152016
drmt: Disaggregated programmable switching
S Chole, A Fingerhut, S Ma, A Sivaraman, S Vargaftik, A Berger, ...
Proceedings of the Conference of the ACM Special Interest Group on Data …, 2017
1902017
Towards programmable packet scheduling
A Sivaraman, S Subramanian, A Agrawal, S Chole, ST Chuang, T Edsall, ...
Proceedings of the 14th ACM workshop on hot topics in networks, 1-7, 2015
732015
Method And Apparatus For Scheduling Matrix Operations In Digital Processing Systems
ST Chuang, SV Chole, SCH Ma
US Patent App. 16/869,520, 2020
42020
Methods and Apparatus for Constructing Digital Circuits for Performing Matrix Operations
SCH Ma, ST Chuang, SV Chole
US Patent App. 16/377,103, 2020
42020
Methods and apparatus for constructing digital circuits for performing matrix operations
SV Chole, ST Chuang, SCH Ma
US Patent 11,983,616, 2024
32024
SparseCore: An accelerator for structurally sparse CNNs
S Chole, R Tadishetti, S Reddy
Proc. SysML Conf, 1-3, 2018
22018
Method and apparatus for efficiently processing convolution neural network operations
ST Chuang, SV Chole, SCH Ma
US Patent 11,151,416, 2021
12021
Methods and apparatus for accessing external memory in a neural network processing system
S Ma, ST Chuang, S Chole
US Patent 12,008,463, 2024
2024
Method and apparatus for using a packet architecture to process neural networks in a neural processing unit
SV Chole, ST Chuang, SCH Ma
US Patent App. 17/970,450, 2024
2024
Dynamic packet buffers with consolidation of low utilized memory banks
SV Chole, ST Chuang, G Akis, F Bonardi, R Pan
US Patent 9,965,211, 2018
2018
dRMT: Disaggregated Programmable Switching (Extended Version)
S Chole, A Fingerhut, S Ma, A Sivaraman, S Vargaftik, A Berger, ...
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